Low frequency noise in 0.12 mum partially and fully depleted SOI technology

Low frequency noise characterisation of 0.12 μm SOI CMOS technology was performed for Partially and Fully Depleted N-MOSFETs. Static performances are first presented, then we address the drain current fluctuations in both linear and saturation regimes. Taking into consideration the usually admitted 1/f noise models in MOS devices and their applicability in our case, we finally point out the enhancement of the extracted trap densities for both architectures compared to previously obtained results in 0.25 μm SOI devices.